It is well known that a scanning electron microscope (SEM) can be used as a tool for studying and determining the cause for failure in an integrated circuit semiconductor device. However, in the present state of the art, it is almost impossible to find, visually, in a scanning electron microscope, the exact location of a defect in an integrated circuit or memory which typically has thousands of circuits and thousands of transistors or memory cells, or the like. The defect could be caused by a very small physical anomaly associated with one transistor or one circuit line. It may be on a top layer or a buried layer. The search for such a defect visually in a SEM can be very time consuming and sometimes practically impossible using presently known techniques.